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ST9040 ? february 1997 16k rom hcmos mcu with eeprom, ram and a/d converter (ordering information at the end of the datasheet) pqfp80 plcc68 register oriented 8/16 bit core with run, wfi and halt modes minimum instruction cycle time : 500ns (12mhz internal) internal memory : rom 16k bytes ram 256 bytes eeprom 512 bytes 224 general purpose registers available as ram, accumulators or index registers (register file) 80-pin pqfp package for ST9040q 68-lead plcc package for ST9040c dma controller, interrupt handler and serial pe- ripheral interface as standard features up to 56 fully programmable i/o pins up to 8 external plus 1 non-maskableinterrupts 16 bit timer with 8 bit prescaler, able to be used as a watchdog timer two 16 bit multifunction timers, each with an 8 bit prescaler and 13 operating modes 8 channel 8 bit analog to digital converter, with analog watchdogs and external references serial communications interface with asynchro- nous and synchronous capability rich instruction set and 14 addressingmodes division-by-zero trap generation versatile developmenttools, including assembler, linker, c-compiler, archiver, graphic oriented de- buggerand hardware emulators real time operating system windowed and one time programmable eprom parts available for prototyping and pre-production developmentphases pin to pin compatible with st9036 1/56
table of contents ST9040 ........................................ ..... 1 1.1 general description . . . . . . ........................ 5 1.2 pin description . . . . . . . . . . ........................ 6 1.2.1 i/o port alternate functions . . ....................... 6 1.3 memory . . . . . ................................. 10 1.3.1 introduction ............................... 10 1.3.2 eeprom . .................................. 10 1.3.2.1 introduction . . . . . . ........................ 10 1.3.2.2 eeprom programming procedure . . ................ 11 1.3.2.3 parallel programming procedure . . . ................ 11 1.3.2.4 eeprom programming voltage . . . ................ 11 1.3.2.5 eeprom programming time . . . . . . . .............. 11 1.3.2.6 eeprom interrupt management . . . ................ 11 1.3.2.7 eeprom control register ...................... 12 1.3.3 register map ............................... 12 2 electrical characteristics .............................. 13 st90e40 / st90t40 ................................... 35 1.1 general description . . . . . . ........................ 38 1.2 pin description . . . . . . . . . . ........................ 39 1.2.1 i/o port alternate functions . . . . . . . . . . . . . . . . . . . . 39 1.1 memory . . ..................................... 42 1.2 eprom programming . . . . . . ........................ 42 1.2.1 eprom erasing ................................ 42 st90r40 ........................................ .... 49 1.1 general description . . . . . . ........................ 51 1.2 pin description . . . . . . . . . . ........................ 52 1.2.1 i/o port alternate functions . . . . . . . . . . . . . . . ..... 52 1.3 memory . . ..................................... 55 ? 2/56
figure 1. 80 pin pqfp package pin name pin name pin name pin name 1av ss 25 p34/t1ina 64 p20/nmi 80 av dd 2 nc 26 p33/t0outb 63 nc 79 nc 3 nc 27 p32/t0inb 62 v ss 78 p47/ain7 4 p44/ain4 28 p31/t0outa 61 p70/sin 77 p46/ain6 5 p57 29 p30/p/d/t0ina 60 p71/sout 76 p45/ain5 6 p56 30 a15 59 p72/int4/txclk /clkout 75 p43/ain3 7 p55 31 a14 74 p42/ain2 8 p54 32 nc 58 p73/int5 /rxclk/adtrg 73 p41/ain1 9 int7 33 a13 72 p40/ain0 10 int0 34 a12 57 p74/p/d/int6 71 p27/rrdy5 11 p53 35 a11 56 p75/wait 70 p26/int3 /rdstb5/p/d 12 nc 36 a10 55 p76/wdout /busreq 13 p52 37 a9 69 p25/wrrdy5 14 p51 38 a8 54 p77/wdin /busack 68 p24/int1 /wrstb5 15 p50 39 p00/a0/d0 16 oscout 40 p01/a1/d1 53 r/w 67 p23/sdo 17 v ss 52 nc 66 p22/int2/sck 18 v ss 51 ds 65 p21/sdi/p/d 19 nc 50 as 20 oscin 49 nc 21 reset 48 v dd 22 p37/t1outb 47 v dd 23 p36/t1inb 46 p07/a7/d7 24 p35/t1outa 45 p06/a6/d6 44 p05/a5/d5 43 p04/a4/d4 42 p03/a3/d3 41 p02/a2/d2 table 1. ST9040q pin description ? ST9040 3/56
pin name pin name pin name pin name 61 p44/ain4 10 p35/t1outa 43 p70/sin 60 av ss 62 p57 11 p34/t1ina 42 p71/sout 59 av dd 63 p56 12 p33/t0outb 41 p72/clkout /txclk/int4 58 p47/ain7 64 p55 13 p32/t0inb 57 p46/ain6 65 p54 14 p31/t0outa 40 p73/adtrg /rxclk/int5 56 p45/ain5 66 int7 15 p30/p/d/t0ina 55 p43/ain3 67 int0 16 p17/a15 39 p74/p/d/int6 54 p42/ain2 68 p53 17 p16/a14 38 p75/wait 53 p41/ain1 l 1 p52 18 p15/a13 37 p76/wdout /busreq 52 p40/ain0 2 p51 19 p14/a12 51 p27/rrdy5 3 p50 20 p13/a11 36 p77/wdin /busack 50 p26/int3 /rdstb5/p/d 4 oscout 21 p12/a10 5v ss 22 p11/a9 35 r/w 49 p25/wrrdy5 6 oscin 23 p10/a8 34 ds 48 p24/int1 /wrstb5 7 reset 24 p00/a0/d0 33 as 8 p37/t1outb 25 p01/a1/d1 32 v dd 47 p23/sdo 9 p36/t1inb 26 p02/a2/d2 31 p07/a7/d7 46 p22/int2/sck 30 p06/a6/d6 45 p21/sdi/p/d 29 p05/a5/d5 44 p20/nmi 28 p04/a4/d4 27 p03/a3/d3 table 2. ST9040c pin description figure 2. 68 pin plcc package ? ST9040 4/56
1.1general description the ST9040 is a rom member of the st9 family of microcontrollers, completely developed and pro- duced by sgs-thomson microelectronics using a proprietary n-well hcmos process. the ST9040 peripheral and functional actions are fully compatible throughout the st903x/4x family. this datasheet will thus provide only information specific to this rom device. the reader is asked to refer to the datasheet of the st9036 rom-based de- vice for further details. the nucleus of the ST9040 is the advanced core which includes the central processing unit (cpu), the register file, a 16 bit timer/watchdog with 8 bit prescaler, a serial peripheral interface support- ing s-bus, i 2 c-bus and im-bus interface,plus two 8 bit i/o ports. the core has independent memory and register buses allowing a high degree of pipe- lining to add to the efficiency of the code execution speed of the extensive instruction set. the power- ful i/o capabilities demanded by microcontroller applications are fulfilled by the ST9040 with up to 56 i/o lines dedicated to digital input/output. these lines are grouped into up to seven 8 bit i/o ports and can be configured on a bit basis under software control to provide timing, status signals, an address/databus for interfacing external mem- ory, timer inputs and outputs, analog inputs, exter- nal interrupts and serial or parallel i/o with or without handshake. three basic memory spaces are available to support this wide range of configurations: program memory (internal and external), data memory (internal and ex- ternal)andtheregisterfile, which includesthecontrol and status registers of the on-chip peripherals. two 16 bit multifunction timers, each with an 8 bit prescaler and 13 operating modes allow simple use for complex waveform generation and meas- urement, pwm functions and many other system timing functionsby the usage of the two associated dma channels for each timer. in addition there is an 8 channel analog to digital converter with inte- gral sample and hold, fast 11 m s conversion time and 8 bit resolution. an analog watchdog feature is included for two input channels. completing the device is a full duplex serial com- munications interface with an integral 110 to 375,000 baud rate generator, asynchronous and 1.5mbyte/s synchronous capability (fully program- mable format) and associated address/wake-up option, plus two dma channels. ? ST9040 5/56
figure 3. ST9040 block diagram 1.2 pin description as. address strobe (output, active low, 3-state). address strobe is pulsed low once at the begin- ning of each memory cycle. the rising edge of as indicates that address, read/write (r/w), and data memory signals are valid for program or data memory transfers. under program control, as can be placed in a high-impedance state along with port 0 and port 1, data strobe (ds) and r/w. ds. data strobe (output, active low, 3-state). data strobe provides the timing for data movement to or from port 0 for each memory transfer. during a write cycle, data out is valid at the leading edge of ds . during a read cycle, data in must be valid prior to the trailing edge of ds. when the ST9040 ac- cesses on-chip memory, ds is held high during the whole memory cycle. it can be placed in a high im- pedancestate alongwith port 0, port 1, as and r/w. r/w. read/write (output, 3-state). read/write determines the direction of data transfer for exter- nal memory transactions. r/w is low when writing to external program or data memory, and high for all other transactions. it can be placed in a high im- pedancestate along with port 0, port 1, as and ds. reset. reset (input, active low). the st9 is initial- isedby the reset signal. with the deactivationof re- set, program execution begins from the program memory location pointed to by the vector contained in program memory locations 00h and 01h. int0, int7 . external interrupts (input, active on ris- ing or falling edge). external interrupt inputs 0 and 7 respectively. int0 channel may also be used for the timer watchdog interrupt. oscin, oscout . oscillator (input and output). these pins connect a parallel-resonant crystal (24mhz maximum), or an external source to the on-chip clock oscillator and buffer. oscin is the in- put of the oscillator inverter and internal clock gen- erator; oscout is the output of the oscillator inverter. av dd . analogv dd ofthe analogto digital converter. av ss. analog v ss of the analog to digital con- verter. must be tied to v ss . v dd . main power supply voltage (5v 10%) v ss . digital circuit ground. p0.0-p0.7, p1.0-p1.7, p2.0-p2.7 p3.0-p3.7, p4.0- p4.7, p5.0-p5.7, p7.0-p7.7 i/o port lines (in- put/output, ttl or cmos compatible) . 56 lines grouped into i/o ports of 8 bits, bit programmable under program control as general purpose i/o or as alternate functions. 1.2.1 i/o port alternate functions each pin of the i/o ports of the ST9040 may as- sume software programmable alternative func- tions as shown in the pin configuration drawings. table 1-3 shows the functions allocated to each i/o port pins and a summary of packagesfor which they are available. cpu 16-bit timer / watchdog + spi sci with dma i/o port 7 (sci) 8 256 bytes register file 2 x 16-bi t timer with dma i/o port 3 ( timers ) 8 i/o port 0 (address/data ) 8 i/o port 1 ( address ) 8 512 bytes eeprom 256 bytes ram 16k bytes rom i/o port 2 ( spi ) 8 i/o port 4 ( analog inputs ) 8 a/d converter i/o port 5 with handshake 8 memory bus register bus vr001385 in t0 int7 av dd av ss ? ST9040 6/56
i/o port name function alternate function pin assignment port. bit plcc pqfp p0.0 a0/d0 i/o address/data bit 0 mux 24 39 p0.1 a1/d1 i/o address/data bit 1 mux 25 40 p0.2 a2/d2 i/o address/data bit 2 mux 26 41 p0.3 a3/d3 i/o address/data bit 3 mux 27 42 p0.4 a4/d4 i/o address/data bit 4 mux 28 43 p0.5 a5/d5 i/o address/data bit 5 mux 29 44 p0.6 a6/d6 i/o address/data bit 6 mux 30 45 p0.7 a7/d7 i/o address/data bit 7 mux 31 46 p1.0 a8 o address bit 8 23 38 p1.1 a9 o address bit 9 22 37 p1.2 a10 o address bit 10 21 36 p1.3 a11 o address bit 11 20 35 p1.4 a12 o address bit 12 19 34 p1.5 a13 o address bit 13 18 33 p1.6 a14 o address bit 14 17 31 p1.7 a15 o address bit 15 16 30 p2.0 nmi i non-maskable interrupt 44 64 p2.0 romless i romless select (mask option) 44 64 p2.1 p/d o program/data space select 45 65 p2.1 sdi i spi serial data out 45 65 p2.2 int2 i external interrupt 2 46 66 p2.2 sck o spi serial clock 46 66 p2.3 sdo o spi serial data in 47 67 p2.4 int1 i external interrupt 1 48 68 p2.4 wrstb5 i handshake write strobe p5 48 68 p2.5 wrrdy5 o handshake write ready p5 49 69 p2.6 int3 i external interrupt 3 50 70 p2.6 rdstb5 i handshake read strobe p5 50 70 p2.6 p/d o program/data space select 50 70 p2.7 rdrdy5 o handshake read ready p5 51 71 p3.0 t0ina i mf timer 0 input a 15 29 p3.0 p/d o program/data space select 15 29 p3.1 t0outa o mf timer 0 output a 14 28 p3.2 t0inb i mf timer 0 input b 13 27 p3.3 t0outb o mf timer 0 output b 12 26 p3.4 t1ina i mf timer 1 input a 11 25 table 3. ST9040 i/o port alternate function summary pin description (continued) ? ST9040 7/56
i/o port name function alternate function pin assignment port. bit plcc pqfp p3.5 t1outa o mf timer 1 output a 10 24 p3.6 t1inb i mf timer 1 input b 9 23 p3.7 t1outb o mf timer 1 output b 8 22 p4.0 ain0 i a/d analog input 0 52 72 p4.1 ain1 i a/d analog input 1 53 73 p4.2 ain2 i a/d analog input 2 54 74 p4.3 ain3 i a/d analog input 3 55 75 p4.4 ain4 i a/d analog input 4 61 4 p4.5 ain5 i a/d analog input 5 56 76 p4.6 ain6 i a/d analog input 6 57 77 p4.7 ain7 i a/d analog input 7 58 78 p5.0 i/o i/o handshake port 5 3 15 p5.1 i/o i/o handshake port 5 2 14 p5.2 i/o i/o handshake port 5 1 13 p5.3 i/o i/o handshake port 5 68 11 p5.4 i/o i/o handshake port 5 65 8 p5.5 i/o i/o handshake port 5 64 7 p5.6 i/o i/o handshake port 5 63 6 p5.7 i/o i/o handshake port 5 62 5 p7.0 sin i sci serial input 43 61 p7.1 sout o sci serial output 42 60 p7.1 romless i romless select (mask option) 42 60 p7.2 int4 i external interrupt 4 41 59 p7.2 txclk i sci transmit clock input 41 59 p7.2 clkout o sci byte sync clock output 41 59 p7.3 int5 i external interrupt 5 40 58 p7.3 rxclk i sci receive clock input 40 58 p7.3 adtrg i a/d conversion trigger 40 58 p7.4 int6 i external interrupt 6 39 57 p7.4 p/d o program/data space select 39 57 p7.5 wait i external wait input 38 56 p7.6 wdout o t/wd output 37 55 p7.6 busreq i external bus request 37 55 p7.7 wdin i t/wd input 36 54 p7.7 busack o external bus acknowledge 36 54 table 4. ST9040 i/o port alternate function summary (continued) pin description (continued) ? ST9040 8/56
applicable for ST9040 dec dec hex 00 00 02 02 03 03 08 08 09 09 10 0a 24 18 63 3f r255 rff reserved reserved port 7 mft 1 reserved mft 0 reserved a/d rff r254 rfe mspi port 3 rfe r253 rfd rfd r252 rfc wcr rfc r251 rfb t/wd reserved reserved rfb r250 rfa port 2 rfa r249 rf9 rf9 r248 rf8 mft rf8 r247 rf7 ext int reserved port 5 mft 1 sci rf7 r246 rf6 port1 rf6 r245 rf5 rf5 r244 rf4 rf4 r243 rf3 reserved reserved mft0 rf3 r242 rf2 port 0 port 4 rf2 r241 rf1 eepromcr rf1 r240 rf0 reserved rf0 table 1-4. group f peripheral organization address spaces ? ST9040 9/56
figure 1-4. memory map 1.3 memory 1.3.1 introduction the memory of the st9 is divided into two spaces: - data memory with up to 64k (65536) bytes - program memory with up to 64k (65536) bytes thus, there is a total of 128k bytes of addressable memory space. the 16k bytes of on-chip rom memory of the ST9040 are selected at memory addresses 0 through 3fffh (hexadecimal) in the program space. the data space includes the 512 bytes of on-chip eeprom at addresses 0 through 1ffh and the 256 bytes of on-chip ram memory at addresses 200h through 2ffh. 1.3.2 eeprom 1.3.2.1 introduction the eeprommemory provides user-programma- ble non-volatile memory on-chip, allowing fast and reliable storage of user data. as there is also no off-chip access required, as for an external serial eeprom, high security levels can be achieved. the eeprom memory is read as normal ram memory at data space addresses 0 to 1ffh, how- ever one wait cycle is automatically added for a read cycle, while a byte write cycle to the eeprom will cause the start of an erase/write cycle at the addressed location. word (16 bit) writes are not allowed. the programming cycle is self-timed, with a typical programming time of 6ms. the voltage necessary for programming the eeprom is internally gener- ated with a +18v charge pump circuit. up to 16 bytes of data may be programmed into the eeprom during the same write cycle by using the parallel write function. a standbymode is also available which disables all power consumption sources within the eeprom for low power requirements. when stby is high, any attempt to access the eeprom memory will produce unpredictable results. after the re-ena- bling of the eeprom, a delay of 6 intclk cycles must be allowed before the selection of the eeprom. the eeprom of the ST9040 has been imple- mented in a high reliability technology developed by sgs-thomson, this, together with the double bit structure,allow 300k erase/write cycles and 10 year data retention to be achieved on a microcon- troller. control of the eeprom is performed through one registermapped at register addressr241 in page 0. ? ST9040 10/56
1.3.2.2 eeprom programming procedure the programming of a byte of eeprommemory is equivalent to writing a byte into a ram location af- ter verifying that eebusy bit is low. instructions operating on word data (16 bits) will not access the eeprom. the eeprom enable bit eewen must first be set before writing to the eeprom. when this bit is low, attempts to write data to the eeprom have no affect, this prevents any spurious memory ac- cesses from affecting the data in the eeprom. termination of the write operation can be detected by polling on the eebusy status bit, or by inter- rupt, taking the interrupt vector from the external interrupt 4 channel. the selection of the interrupt is made by eeprom interrupt enable bit eeien. it should be noted that the mask bit of external inter- rupt 4 should be set, and the interrupt pending bit reset, before the setting of eeien to prevent un- wanted interrupts. a delay (eg a nop instruction) should also be included between the operationson the mask and pending bits of external interrupt 4. if polling on eebusy is used, a delay of 6 intclk clock cycles is necessary after the end of program- ming, this can be a nop instruction or, normally, therequired time to test the eebusy bit and to branch to the next instruction will be sufficient. while eebusy is active, any attempt to access the eeprom matrix will be aborted and the data read will be invalid. eebusy is a read only bit and can- not be reset by the user if active. an erased bit of the eeprom memory will read as a logic a0o, while a programmed cell will be read as a logic a1o. for applications requiring the highest level of reliability, the verify mode, set by eeprom control register bit vrfy, allows the reading of the eeprom memory cells with a reduced gate volt- age (typically 20%). if the eeprom memory cell has been correctly programmed, a logic a1o will be read with the reduced voltage,otherwise a logic a0o will be read. 1.3.2.3 parallel programming procedure parallel programming is a feature of the eeprom macrocell. one up to sixteen bytes of a same row can be programmed at once. the constraint is that each of the bytes occur in the same row of the eeprom memory (a4 constant, a3-a0 variable). to operate this mode, the parallel mode enable bit, pllen, must be set. the data written is then latched into buffers (at the ad- dresses specified, which may be non-sequential) and then transferred to the eeprom memory by the setting of the pllst bit of the control register. both pllst and pllen are internally reset at the end of the programming cycle. any attempt to read the eeprom memory when pllen is set will give invalid data. in the event that the data in the buffer latches is not required to be written into the memory by the setting of pllst, the correct way to terminate the operation is to reset pllen and to perform a dummy read of theeeprommemory. this termina- tion will clear all data present in the latches. 1.3.2.4 eeprom programming voltage no external vpp voltage is required, an internal 18volt charge-pump gives the required energy by a dedicated oscillator pumping at a typical fre- quency of 5mhz, regardless of the external clock. 1.3.2.5 eeprom programming time no timing routine is required to control the pro- gramming time as dedicated circuitry takes care of the eeprom programming time (the typical pro- gramming time is 6ms). 1.3.2.6 eeprom interrupt management at the end of each write procedure the eeprom sends an interrupt request (if eeien bit is set). the eeprom shares its interrupt channel with the ex- ternal interrupt source int4, from which the priority level is derived. care must be taken when eeien is reset. the as- sociated external interrupt channel must be dis- abled (by reseting bit 4 of eimr, r244) along with reseting the interrupt pending bit (bit 4 of eipr, r243) to prevent unwanted interrupts. a delay in- struction (at least 1 nop instruction) must be in- serted between these two operations warning. the content of the eeprom of the ST9040 family after the out-going test at sgs- thomson's manufacturing location is not guar- enteed. eeprom (continued) ? ST9040 11/56
figure 1-5. eeprom parallel programming rows eeprom (continued) 1.3.2.7 eeprom control register eecr r241 (f1h) page 0 read/write (except eebusy: read only) eeprom control register reset value : 0000 0000b (00h) 70 0 verify eestby eeien pllst pllen eebusy eewen bit 7 = b7: this bit is forced to a0o after reset and must not be modified by the user. bit 6 = verify: set verify mode . verify (active high) is used to activate the verify mode. the verify mode provides a guarentee of good re- tention of the programmed bit. when active, the reading voltage on the cell gate is decreased from 1.2v to 0.0v, decreasing the current from the pro- grammed cell by 20%. if the cell is well pro- grammed (to a1o), a a1o will still be read, otherwise a a0o will be read. note . the verify mode must not be used during an erasing or a programming cycle). bit 5 = eestby: eeprom stand-by . eestby = a1o switches off all power consumption sources in- side the eeprom. any attempt to access the eeprom when eestby = a1o will produce unpre- dictable results. note. after eestby is reset, the user must wait 6 cpuclk cycles (e.g. 1 nop instruction) before se- lecting the eeprom. bit 4 = eeien: eeprom interrupt enable . inten = a1o disables the external interrupt source int4, and enables the eeprom to send its interrupt re- quest to the central interrupt unit at the end of each write procedure. bit 3 = pllst: parallel write start . setting pllst to a1o starts the parallel writing procedure.it can be set only if pllen is alreadyset. pllst is internally reset at the end of the programming sequence. bit 2 = pllen: parallel write enable . setting pllen to a1o enables the parallel writing mode which allows the user to write up to 16 bytes at the same time. pllen is internally reset at the end of the programming sequence. bit 1 = eebusy: busy . when this read only bit is high, an eeprom write operation is in progress and any attempt to access the eeprom is aborted. bit 0 = eewen: eeprom write enable . setting this bit allows programming of the eeprom, when low a writing attempt has no effect. 1.3.3 register map please refer to the register map of the st9036 for all general registers with the exceptionof the regis- ter shown in the following table. eecr r241 (f1h) page 0 read/write control registers table 1-5. register map addendum ? ST9040 12/56
2 electrical characteristics symbol parameter value unit v dd supply voltage 0.3 to 7.0 v av dd ,av ss analog supply voltage v ss =av ss ST9040 13/56
symbol parameter test conditions value unit min. typ. max. v ihck clock input high level external clock 0.7 v dd v dd + 0.3 v v ilck clock input low level external clock 0.3 0.3 v dd v v ih input high level ttl 2.0 v dd + 0.3 v cmos 0.7 v dd v dd + 0.3 v v il input low level ttl 0.3 0.8 v cmos 0.3 0.3 v dd v v ihrs reset input high level 0.7 v dd v dd + 0.3 v v ilrs reset input low level 0.3 0.3 v dd v v hyrs reset input hysteresis 0.3 1.5 v v oh output high level push pull, iload = 0.8ma v dd 0.8 v v ol output low level push pull or open drain, iload = 1.6ma 0.4 v i wpu weak pull-up current bidirectional weak pull- up, v ol =0v 50 200 420 m a i apu active pull-up current, for int0 and int7 only v in < 0.8v, under reset 80 200 420 m a i lkio i/o pin input leakage input/tri-state, 0v < v in ST9040 14/56
symbol parameter test conditions value unit min. typ. max. i dd run mode current no cpuclk prescale, clock divide by 2 24mhz, note 1 40 ma i dp2 run mode current prescale by 2 clock divide by 2 24mhz, note 1 30 ma i wfi wfi mode current no cpuclk prescale, clock divide by 2 24mhz, note 1 20 ma i halt halt mode current 24mhz, note 1 100 m a note 1: all i/o ports are configured in bidirectional weak pull-up mode with no dc load, external clock pin (oscin) is driven by square wave external clock. no peripheral working. ac electrical characteristics (v dd =5v 10% t a =40 cto+85 c, unless otherwise specified) ? ST9040 15/56
n symbol parameter value unit note min. max. 1 tpc oscin clock period 41.5 ns 1 83 ns 2 2 trc, tfc oscin rise and fall time 12 ns 3 twcl, twch oscin low and high width 17 25 ns 1 38 ns 2 notes: 1. clock divided by 2 internally (moder.div2=1) 2. clock not divided by 2 internally (moder.div2=0) clock timing table (v dd =5v 10%, t a =40 cto+85 c, intclk = 12mhz, unless otherwise specified) clock timing ? ST9040 16/56
n symbol parameter value (note) unit oscin divided by 2 oscin not divided by 2 min. max. 1 tsa (as) address set-up time before as tpc (2p+1) 22 twch+ptpc 18 20 ns 2 thas (a) address hold time after as tpc 17 twcl 13 25 ns 3 tdas (dr) as to data available (read) tpc (4p+2w+4) 52 tpc (2p+w+2) 51 115 ns 4 twas as low pulse width tpc (2p+1) 7 twch+ptpc 3 35 ns 5 tdaz (ds) address float to ds t12 12 12ns 6 twdsr ds low pulse width (read) tpc (4p+2w+3) 20 twch+tpc (2p+w+1) 16 105 ns 7 twdsw ds low pulse width (write) tpc (2p+2w+2) 13 tpc (p+w+1) 13 70 ns 8 tddsr (dr) ds todata valid delay (read) tpc (4p+2w-3) 50 twch+tpc(2p+w+1) 46 75 ns 9 thdr (ds) data to ds hold time (read) 0 0 0 ns 10 tdds (a) ds to address active delay tpc 7 twcl 3 35 ns 11 tdds (as) ds to as delay tpc 18 twcl 14 24 ns 12 tsr/w (as) r/w set-up time before as tpc (2p+1) 22 twch+ptpc 18 20 ns 13 tddsr (r/w) ds to r/w and address not valid delay tpc 9 twcl 5 33 ns 14 tddw (dsw) write data valid to ds delay (write) tpc (2p+1) 32 twch+ptpc 28 10 ns 15 thds (dw) data hold time after ds (write) tpc 9 twcl 5 33 ns 16 tda (dr) address valid to data valid delay (read) tpc (6p+2w+5) 68 twch+tpc (3p+w+2) 64 140 ns 17 tdas (ds) as to ds delay tpc 18 twcl 14 24 ns external bus timing table ( v dd =5v 10%,t a = 40 cto+85 c, cload = 50pf, cpuclk = 12mhz, unless otherwise specified) external wait timing table (v dd =5v 10%,t a = 40 cto+85 c, cload = 50pf, intclk = 12mhz, push-pull output configuration, unless otherwise specified) n symbol parameter value (note) unit oscin divided by 2 oscin not divided by 2 min. max. 1 tdas (wait) as to wait delay 2(p+1)tpc 29 2(p+1)tpc 29 40 ns 2 tdas (wait) as to wait min. delay 2(p+w+1)tpc 4 2(p+w+1)tpc 4 80 ns 3 tdas (wait) as to wait max. delay 2(p+w+1)tpc 29 2(p+w+1)tpc 29 83w+ 40 ns note: (for both tables) the value in the left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. the value in the right hand two columns show the timing minimum and maximum for an external clock at 24 mhz divided by 2, prescaler value of zero and zero wait status. legend: tpc =oscin period p = clock prescaling value twch =high level oscin half period w = wait cycles twcl =low level oscin half period ? ST9040 17/56
external bus timing external wait timing ? ST9040 18/56
n symbol parameter value (note) min. max. unit oscin divided by 2 oscin not divided by 2 min. max. min. max. 1 twrdy rdrdy, wrrdy pulse width in one line handshake 2tpc (p+w+1) 18 tpc (p+w+1) 18 65 ns 2 twstb rdstb, wrstb pulse width 2tpc+12 tpc+12 95 ns 3 tdst (rdy) rdstb, or wrstb to rdrdy or wrrdy tpc+45 (tpc-twcl) +45 87 ns 4 tspd (rdy) port data to rdrdy set-up time (2p+2w+1) tpc 25 twch+ (w+p) tpc 25 16 ns 5 tspd (rdy) port data to wrrdy set-up time in one line handshake 43 43 43 ns 6 thpd (rdy) port data to wrrdy hold time in one line handshake 000ns 7 tspd (stb) port data to wrstb set-up time 10 10 10 ns 8 thpd (stb) port data to wrstb hold time 25 25 25 ns 9 tdstb (pd) rdstbd to port data delay time in bidirectional handshake 35 35 35 ns 10 tdstb (phz) rdstb to port high-z delay time in bidirectional handshake 25 25 25 ns note: the value in the left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. the value in the right hand two columns show the timing minimum and maximum for an external clock at 24 mhz divided by 2, prescaler value of zero and zero wait status. legend: p = clock prescaling value (r235.4,3,2) w = programmable wait cycles (r252.2.1.0/5,4,3) + external wait cycles handshake timing table (v dd =5v 10%, t a =40 cto+85 c, cload = 50pf, intclk = 12mhz, push-pull output configuration, unless otherwise specified) ? ST9040 19/56
handshake timing ? ST9040 20/56
n symbol parameter value (note) unit oscin divided by 2 oscin not divided by 2 min . max . 1 tdbr (back) breq to busack tpc+8 twcl+12 50 ns tpc(6p+2w+7)+65 tpc(3p+w+3)+twcl+65 360 ns 2 tdbr (back) breq to busack 3tpc+60 tpc+twcl+60 185 ns 3 tdback (brel) busack to bus release 20 20 20 ns 4 tdback (bact) busack to bus active 20 20 20 ns note: the value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. the value right hand two columns show the timing minimum and maximum for an external clock at 24mhz divided by 2, prescale value of zero and zero wait status. bus request/acknowledge timing table (v dd =5v 10%,t a =40 cto+85 c, cload = 50pf, intclk = 12mhz, push-pull output configuration, unless otherwise specified) note : memint = group of memory interface signals: as, ds, r/w, p00-p07, p10-p17 bus request/acknowledge timing ? ST9040 21/56
n symbol parameter value (note) unit oscin divided by 2 min. oscin not divided by 2 min. min. max. 1 twlr low level minimum pulse width in rising edge mode 2tpc+12 tpc+12 95 ns 2 twhr high level minimum pulse width in rising edge mode 2tpc+12 tpc+12 95 ns 3 twhf high level minimum pulse width in falling edge mode 2tpc+12 tpc+12 95 ns 4 twlf low level minimum pulse width in falling edge mode 2tpc+12 tpc+12 95 ns note: the value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. the value right hand two columns show the timing minimum and maximum for an external clock at 24 mhz divided by 2, prescale value of zero and zero wait status. external interrupt timing table (v dd =5v 10%, t a =40 cto+85 c, cload = 50pf, intclk = 12mhz, push-pull output configuration, unless otherwise specified) external interrupt timing ? ST9040 22/56
n symbol parameter value unit min. max. 1 tsdi input data set-up time 100 ns 2 thdi (1) input data hold time 1/2 tpc+100 ns 3 tdov sck to output data valid 100 ns 4 thdo output data hold time -20 ns 5 twskl sck low pulse width 300 ns 6 twskh sck high pulse width 300 ns note: tpc is the oscin clock period. spi timing table (v dd =5v 10%, t a = 40 c to +85 c, cload = 50pf, intclk = 12mhz, output alternate function set as push-pull) spi timing ? ST9040 23/56
watchdog timing n symbol parameter values unit min. max. 1 twwdol wdout low pulse width 620 ns 2 twwdoh wdout high pulse width 620 ns 3 twwdil wdin high pulse width 350 ns 4 twwdih wdin low pulse width 350 ns watchdog timing table( v dd =5v 10%, t a =40 cto+85 c, cload = 50pf, cpuclk = 12mhz, push-pull output configuration, unless otherwise specified ) ? ST9040 24/56
n symbol parameter oscin divided by 2 (1) oscin not divided (1) value (2) unit min. max. min. max. min. max. 1t low external trigger pulse width 2xt pc t pc 83 ns 2t high external trigger pulse 2xt pc t pc 83 ns 3t ext external trigger active edges distance 138xt pc 69xt pc 5.75 m s 4t str internal delay between extrg falling edge and first conversion start t pc 3xt pc 0.5xtpc 1.5xt pc 41.5 125 ns notes: 1. variable clock (t pc =oscin clock period) 2. intclk=12mhz external trigger timing (v dd =5v 10%, t a = 40 c to +85 c, cload = 50pf) a/d external trigger timing a/d converter ? ST9040 25/56
n symbol parameter oscin divided by 2 (2) oscin not divided by 2 (2) value (3) unit min. max. min. max. min. max. 1tw high internal trigger pulse width tpc .5 x tpc 41.5 - ns 2tw low internal trigger pulse distance 6 x tpc 3 x tpc 250 - ns 3tw ext internal trigger active edges distance (1) 276n x tpc 138n x tpc n x 11.5 - m s 4tw str internal delay between intrg rising edge and first conversion start tpc 3 x tpc .5 x tpc 1.5 x tpc 41.5 125 ns a/d internal trigger timing table a/d internal trigger timing ? ST9040 26/56
n symbol parameter oscin divided by 2 (2) oscin not divided by 2 (2) value (3) unit min. max. min. max. min. max. 1tw ext cen pulse width (1) 276n x tpc 138n x tpc n x 11.5 - m s notes: 1. n = number of autoscanned channels (1 < n < 8) 2. variable clock (tpc = oscin clock period) 3. cpuclk = 12mhz a/d channel enable timing table a/d channel enable timing ? ST9040 27/56
parameter typical (1) minimum maximum units (2) notes analog input range a vcc 3 a vcc v cc v conversion time 11.5 m s (3, 4) sample time 3 m s (3) power-up time 60 m s resolution 8 8 bits monotonicity guaranteed no missing codes guaranteed zero input reading 00 hex full scale reading ff hex offset error .5 1 lsbs (2,6) gain error .5 1 lsbs (6) diff. non linearity .3 .2 .5 lsbs (6) int. non linearity 1 lsbs (6) absolute accuracy 1 lsbs (6) s/n 45 49 db a vcc /a vss resistance 13.5 16 11 k w input resistance 12 8 15 k w (5) hold capacitance 30 pf input leakage 3 m a notes: 1. the values are expected at 25 degree centigrade with a vcc =5v 2. alsbso, as used here, has a value of a vcc /256 3. @ 12mhz internal clock 4. including sample time 5. it must be intended as the internal series resistance before the sampling capacitor 6. this is a typical expected value, but not a tested production parameter. if v(i) is the value of the i-th transition level (0 < i < 254), the performance of the a/d co nverter has been valued as follows: offset error = deviation between the actual v(0) and the ideal v(0) (=1/2 lsb) gain error = deviation between the actual v(254) and the ideal v(254) (=avcc-3/2 lsb) dnl error = max {[v(i) - v(i-1)]/lsb - 1} inl error = max {[v(i) - v(0)]/lsb - i} a/d analog specifications ? ST9040 28/56
multifunction timer unit external timing n symbol parameter oscin divided by 2 (3) oscin not divided by 2 (3) value (4) unit note min. max. 1tw ctw external clock/trigger pulse width 2n x tpc n x tpc n x 83 - ns 1 2tw ctd external clock/trigger pulse distance 2n x tpc n x tpc n x 83 - ns 1 3tw aed distance between two active edges 6 x tpc 3 x tpc 249 - ns 4tw gw gate pulse width 12 x tpc 6 x tpc 498 - ns 5tw lba distance between tinb pulse edge and the following tina pulse edge 2 x tpc tpc 83 - ns 2 6tw lab distance between tina pulse edge and the following tinb pulse edge 00-ns2 7tw ad distance between two txina pulses 0 0 - ns 2 8tw owd minimum output pulse width/distance 6 x tpc 3 x tpc 249 - ns notes: 2.in autodiscrimination mode 1. n = 1 if the input is rising or falling edge sensitive 3.variable clock ( tpc = oscin period ) n = 3 if the input is rising and falling edge sensitive 4.intclk = 12 mhz multifunction timer unit external timing table ? ST9040 29/56
n symbol parameter condition value unit min. max. f rxckin frequency of rxckin 1 x mode f ck /8 hz 16 x mode f ck /4 hz tw rxckin rxckin shortest pulse 1 x mode 4 t ck s 16 x mode 2 t ck s f txckin frequency of txckin 1 x mode f ck /8 hz 16 x mode f ck /4 hz tw txckin txckin shortest pulse 1 x mode 4 t ck s 16 x mode 2 t ck s 1ts ds ds (data stable) before rising edge of rxckin 1 x mode reception with rxckin t pc /2 ns 2td d1 txckin to data out delay time 1 x mode transmission with external clock c load <100pf 2.5 t pc ns 3td d2 clkout to data out delay time 1 x mode transmission with clkout 350 ns note: f ck = 1/t ck sci timing table (v dd =5v 10%, t a =- 40 c to +85 c, cload = 50pf, intclk = 12mhz, output alternate function set as push-pull) sci timing ? ST9040 30/56
80-pin plastic quad flat package package mechanical data dim. mm inches min typ max min typ max a 3.40 0.134 a2 2.55 2.80 3.05 0.100 0.110 0.120 d 22.95 23.20 24.45 0.903 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.40 0.724 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.00 0.472 e 0.80 0.032 number of pins n80 nd 24 ne 16 short footprint measurement short footprint recommended padding ? ST9040 31/56
sales type frequency temperature range package ST9040q1/xx 24mhz 0 cto +70 c pqfp80 ST9040c1/xx plcc68 ST9040c6/xx -40 cto+85 c plcc68 note: oxxo is the rom code identifier that is allocated by sgs-thomson after receipt of all requi red options and the related rom file. ordering information 68-pin plastic leadless chip carrier dim. mm inches min typ max min typ max a 4.20 5.08 0.165 0.200 a1 0.51 0.020 a3 2.29 3.30 0.090 0.130 b------ b1------ d 25.02 25.27 0.985 0.995 d1 24.13 24.33 0.950 0.958 d3 20.32 0.800 e 25.02 25.27 0.985 0.995 e1 24.13 24.33 0.950 0.958 e3 20.32 0.800 k1------ h e 1.27 0.050 number of pins n68 nd 16 ne 16 ? ST9040 32/56
ST9040 standard option list please copy this page (enlarge if possible) and complete all sections. send the form, with the rom code image required, to your local sgs-thomson sales office. customer company : [ .................................................. ................ ] company address : [ .................................................. ................ ] [ .................................................. ................ ] telephone : [ .......................... ] fax : [ .......................... ] contact : [ .......................... ] telephone (direct) : [ .......................... ] please confirm characteristics of device : device ST9040 package [ ] pqfp80 [ ] plcc68 temperature range [ ] -40 c to +85 c[]0 c to +70 c special marking [ ] no [ ] yes 14 characters [ | | | | | ||||||||] authorized characters are letters, digits, '.', '-', '/' and spaces only. please consult your local sgs-thomson sales office for other marking details if required. notes : code : [ ] eprom (27128, 27256) [ ] hex format files on ibm-pc ? compatible disk filename : [ ...................... ] confirmation : [ ] code checked with eprom device in application yearly quantity forecast : [ ........................... ] k units - for a period of : [ ........................... ] years preferred production start dates : [ ....................... ] (yy/mm/dd) customer signature : date : ? ST9040 33/56
notes : ? ST9040 34/56
st90e40 st90t40 ? 16k eprom hcmos mcu with eeprom, ram and a/d converter (ordering information at the end of the datasheet) pqfp80 plcc68 register oriented 8/16 bit core with run, wfi and halt modes minimum instruction cycle time: 500ns (12mhz internal) internal memory : eprom 16kbytes ram 256 bytes eeprom 512 bytes 224 general purpose registers available as ram, accumulators or index pointers (register file) 80-pin plastic quad flat pack package for st90t40q 68-lead plastic leaded chip carrier package for st90t40c 80-pin windowed ceramic quad flat pack package for st90e40g 68-lead windowed ceramic leadedchip carrier package for st90e40l dma controller, interrupt handler and serial pe- ripheral interface as standard features 56 fully programmable i/o pins up to 8 external plus 1 non-maskableinterrupts 16 bit timer with 8 bit prescaler, able to be used as a watchdog timer two 16 bit multifunction timers, each with an 8 bit prescaler and 13 operating modes 8 channel 8 bit analog to digital converter, with analog watchdogs and external references serial communications interface with asynchro- nous and synchronous capability rich instruction set and 14 addressingmodes division-by-zero trap generation versatile development tools,including assembler, linker, c-compiler, archiver, graphic oriented de- buggerand hardware emulators real time operating system compatible with st9036 and ST9040 16k rom devices cqfp80w march 1994 clcc68w 35/56
figure 1. 80 pin qfp package pin name pin name pin name pin name 1av ss 25 p34/t1ina 64 p20/nmi 80 av dd 2 nc 26 p33/t0outb 63 nc 79 nc 3 nc 27 p32/t0inb 62 v ss 78 p47/ain7 4 p44/ain4 28 p31/t0outa 61 p70/sin 77 p46/ain6 5 p57 29 p30/p/d/t0ina 60 p71/sout 76 p45/ain5 6 p56 30 p17/a15 59 p72/int4/txclk /clkout 75 p43/ain3 7 p55 31 p16/a14 74 p42/ain2 8 p54 32 nc 58 p73/int5 /rxclk/adtrg 73 p41/ain1 9 int7 33 p15/a13 72 p40/ain0 10 int0 34 p14/a12 57 p74/p/d/int6 71 p27/rrdy5 11 p53 35 p13/a11 56 p75/wait 70 p26/int3 /rdstb5/p/d 12 nc 36 p12/a10 55 p76/wdout /busreq 13 p52 37 p11/a9 69 p25/wrrdy5 14 p51 38 p10/a8 54 p77/wdin /busack 68 p24/int1 /wrstb5 15 p50 39 p00/a0/d0 16 oscout 40 p01/a1/d1 53 r/w 67 p23/sdo 17 v ss 52 nc 66 p22/int2/sck 18 v ss 51 ds 65 p21/sdi/p/d 19 nc 50 as 20 oscin 49 nc 21 reset/v pp 48 v dd 22 p37/t1outb 47 v dd 23 p36/t1inb 46 p07/a7/d7 24 p35/t1outa 45 p06/a6/d6 44 p05/a5/d5 43 p04/a4/d4 42 p03/a3/d3 41 p02/a2/d2 table 1. st90e40g-st90t40qpin description ? st90e40 - st90t40 36/56
pin name pin name pin name pin name 61 p44/ain4 10 p35/t1outa 43 p70/sin 60 av ss 62 p57 11 p34/t1ina 42 p71/sout 59 av dd 63 p56 12 p33/t0outb 41 p72/clkout /txclk/int4 58 p47/ain7 64 p55 13 p32/t0inb 57 p46/ain6 65 p54 14 p31/t0outa 40 p73/adtrg /rxclk/int5 56 p45/ain5 66 int7 15 p30/p/d/t0ina 55 p43/ain3 67 int0 16 p17/a15 39 p74/p/d/int6 54 p42/ain2 68 p53 17 p16/a14 38 p75/wait 53 p41/ain1 l 1 p52 18 p15/a13 37 p76/wdout /busreq 52 p40/ain0 2 p51 19 p14/a12 51 p27/rrdy5 3 p50 20 p13/a11 36 p77/wdin /busack 50 p26/int3 /rdstb5/p/d 4 oscout 21 p12/a10 5v ss 22 p11/a9 35 r/w 49 p25/wrrdy5 6 oscin 23 p10/a8 34 ds 48 p24/int1 /wrstb5 7 reset/v pp 24 p00/a0/d0 33 as 8 p37/t1outb 25 p01/a1/d1 32 v dd 47 p23/sdo 9 p36/t1inb 26 p02/a2/d2 31 p07/a7/d7 46 p22/int2/sck 30 p06/a6/d6 45 p21/sdi/p/d 29 p05/a5/d5 44 p20/nmi 28 p04/a4/d4 27 p03/a3/d3 table 2. st90e40l-st90t40c figure 2. 68 pin lcc package ? st90e40 - st90t40 37/56
figure 3. st90e40 block diagram 1.1 general description the st90e40 and st90t40 (following mentioned as st90e40)are eprom members ofthe st9 fam- ilyof microcontrollers, in windowed ceramic (e) and plastic otp (t) packages respectively, completely developed and produced by sgs-thomson mi- croelectronics using a n-well proprietary hcmos process. the eprom parts are fully compatible with their rom versions and this datasheet will thus provide only information specific to the eprom based de- vices. the reader is asked to refer to the datasheet of the ST9040 rom-based de- vice for further details. the eprom st90e40 may be used for the proto- typing and pre-production phases of development, and can be configured as: a standalone microcon- troller with 16k bytes of on-chip eprom, a micro- controller able to manageexternal memory, or as a parallel processing element in a system with other processors and peripheral controllers. the nucleus of the st90e40 is the advanced core which includes the central processing unit (cpu), the register file, a 16 bit timer/watchdog with 8 bit prescaler, a serial peripheral interface support- ing s-bus, i 2 c-bus and im-bus interface,plus two 8 bit i/o ports. the core has independent memory and register buses allowing a high degree of pipe- lining to add to the efficiency of the code execution speed of the extensive instruction set. the powerful i/o capabilities demanded by micro- controller applications are fulfilled by the st90e40 with up to 56 i/o lines dedicated to digital in- put/output. these lines are grouped into up to seven 8 bit i/o ports and can be configured on a bit basis under software control to provide timing, status signals, an address/data bus for interfacing external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel i/o with or without handshake. cpu 1 6-bit timer / watchdog + spi sci with dma i/o port 7 (sci) 8 256 bytes register file 2 x 16-bit timer w ith dm a i/o port 3 ( timers ) 8 i/o port 0 ( address/data ) 8 i/o port 1 ( address ) 8 512 bytes eeprom 256 bytes ram 16k bytes eprom i/o port 2 ( spi ) 8 i/o port 4 ( ana log inpu ts ) 8 a/d converter i/o port 5 with handshake 8 memory bus register bus vr0a1385 int0 int7 av dd av ss ? st90e40 - st90t40 38/56
three basic memory spaces are available to sup- port this wide range of configurations: program memory (internal and external),data memory (ex- ternal) and the register file, which includes the control and status registers of the on-chip peripher- als. two 16 bit multifunction timers, each with an 8 bit prescaler and 13 operating modes allow simple use for complex waveform generation and meas- urement, pwm functions and many other sys- temmsiming functions by the usage of the two associated dma channels for each timer. in addition there is an 8 channel analog to digital converter with integral sample and hold, fast 11 m s conversion time and 8 bit resolution. an analog watchdog feature is included for two input chan- nels. completing the device is a full duplex serial com- munications interface with an integral 110 to 375,000 baud rate generator, asynchronous and 1.5mbyte/s synchronous capability (fully program- mable format) and associated address/wake-up option, plus two dma channels. 1.2 pin description as. address strobe (output, active low, 3-state). address strobe is pulsed low once at the begin- ning of each memory cycle. the rising edge of as indicates that address, read/write (r/w), and data memory signals are valid for program or data memory transfers. under program control, as can be placed in a high-impedance state along with port 0 and port 1, data strobe (ds) and r/w. ds. data strobe (output, active low, 3-state). data strobe provides the timing for data movement to or from port 0 for each memory transfer. during a write cycle, data out is valid at the leading edge of ds. during a readcycle, datain must be valid prior to the trailing edge of ds. when the ST9040 accesseson- chipmemory, ds is held high during the wholemem- ory cycle. it can be placed in a high impedancestate along with port 0, port 1, as andr/w. r/w. read/write (output, 3-state). read/write de- termines the direction of data transfer for external memorytransactions.r/w is low when writing to ex- ternal program or data memory,and high for all other transactions. it can be placed in a high impedance state along with port 0, port 1, as and ds. reset/v pp . reset (input, active low) or v pp (in- put). the st9 is initialised by the reset signal. with the deactivation of reset, program execu- tion begins from the program memory location pointed to by the vector contained in program memory locations 00h and 01h. in the eprom programming mode, this pin acts as the program- ming voltage input vpp. int0, int7. externalinterrupts (input, active on ris- ing or falling edge). external interrupt inputs 0 and 7 respectively. int0 channel may also be used for the timer watchdog interrupt. oscin, oscout . oscillator (input and output). these pins connect a parallel-resonant crystal (24mhz maximum), or an external source to the on-chip clock oscillator and buffer. oscin is the in- put of the oscillator inverter and internal clock gen- erator; oscout is the output of the oscillator inverter. av dd . analog v dd of the analog to digital con- verter. av ss. analog v ss of the analog to digital con- verter. must be tied to v ss. v dd . main power supply voltage (5v 10%) v ss . digital circuit ground. p0.0-p0.7, p1.0-p1.7, p2.0-p2.7 p3.0-p3.7, p4.0- p4.7, p5.0-p5.7, p7.0-p7.7 i/o port lines (in- put/output, ttl or cmos compatible) . 56 lines grouped into i/o ports of 8 bits, bit programmable under program control as general purpose i/o or as alternate functions. 1.2.1 i/o port alternate functions each pin of the i/o ports of the st90e40/t36 may assume software programmable alternative func- tions as shown in the pin configuration tables. due to bonding options for the packages, some functions may not be present, table 3 shows the functions allocatedto each i/o port pin and a sum- mary of packages for which they are available. general description (continued) ? st90e40 - st90t40 39/56
i/o port name function alternate function pin assignment port. bit plcc pqfp p0.0 a0/d0 i/o address/data bit 0 mux 24 39 p0.1 a1/d1 i/o address/data bit 1 mux 25 40 p0.2 a2/d2 i/o address/data bit 2 mux 26 41 p0.3 a3/d3 i/o address/data bit 3 mux 27 42 p0.4 a4/d4 i/o address/data bit 4 mux 28 43 p0.5 a5/d5 i/o address/data bit 5 mux 29 44 p0.6 a6/d6 i/o address/data bit 6 mux 30 45 p0.7 a7/d7 i/o address/data bit 7 mux 31 46 p1.0 a8 o address bit 8 23 38 p1.1 a9 o address bit 9 22 37 p1.2 a10 o address bit 10 21 36 p1.3 a11 o address bit 11 20 35 p1.4 a12 o address bit 12 19 34 p1.5 a13 o address bit 13 18 33 p1.6 a14 o address bit 14 17 31 p1.7 a15 o address bit 15 16 30 p2.0 nmi i non-maskable interrupt 44 64 p2.0 romless i romless select (mask option) 44 64 p2.1 p/d o program/data space select 45 65 p2.1 sdi i spi serial data out 45 65 p2.2 int2 i external interrupt 2 46 66 p2.2 sck o spi serial clock 46 66 p2.3 sdo o spi serial data in 47 67 p2.4 int1 i external interrupt 1 48 68 p2.4 wrstb5 i handshake write strobe p5 48 68 p2.5 wrrdy5 o handshake write ready p5 49 69 p2.6 int3 i external interrupt 3 50 70 p2.6 rdstb5 i handshake read strobe p5 50 70 p2.6 p/d o program/data space select 50 70 p2.7 rdrdy5 o handshake read ready p5 51 71 p3.0 t0ina i mf timer 0 input a 15 29 p3.0 p/d o program/data space select 15 29 p3.1 t0outa o mf timer 0 output a 14 28 p3.2 t0inb i mf timer 0 input b 13 27 p3.3 t0outb o mf timer 0 output b 12 26 p3.4 t1ina i mf timer 1 input a 11 25 table 3. st90e40, t40 i/o port alternate function summary pin description (continued) ? st90e40 - st90t40 40/56
i/o port name function alternate function pin assignment port. bit plcc pqfp p3.5 t1outa o mf timer 1 output a 10 24 p3.6 t1inb i mf timer 1 input b 9 23 p3.7 t1outb o mf timer 1 output b 8 22 p4.0 ain0 i a/d analog input 0 52 72 p4.1 ain1 i a/d analog input 1 53 73 p4.2 ain2 i a/d analog input 2 54 74 p4.3 ain3 i a/d analog input 3 55 75 p4.4 ain4 i a/d analog input 4 61 4 p4.5 ain5 i a/d analog input 5 56 76 p4.6 ain6 i a/d analog input 6 57 77 p4.7 ain7 i a/d analog input 7 58 78 p5.0 i/o i/o handshake port 5 3 15 p5.1 i/o i/o handshake port 5 2 14 p5.2 i/o i/o handshake port 5 1 13 p5.3 i/o i/o handshake port 5 68 11 p5.4 i/o i/o handshake port 5 65 8 p5.5 i/o i/o handshake port 5 64 7 p5.6 i/o i/o handshake port 5 63 6 p5.7 i/o i/o handshake port 5 62 5 p7.0 sin i sci serial input 43 61 p7.1 sout o sci serial output 42 60 p7.1 romless i romless select (mask option) 42 60 p7.2 int4 i external interrupt 4 41 59 p7.2 txclk i sci transmit clock input 41 59 p7.2 clkout o sci byte sync clock output 41 59 p7.3 int5 i external interrupt 5 40 58 p7.3 rxclk i sci receive clock input 40 58 p7.3 adtrg i a/d conversion trigger 40 58 p7.4 int6 i external interrupt 6 39 57 p7.4 p/d o program/data space select 39 57 p7.5 wait i external wait input 38 56 p7.6 wdout o t/wd output 37 55 p7.6 busreq i external bus request 37 55 p7.7 wdin i t/wd input 36 54 p7.7 busack o external bus acknowledge 36 54 table 4. st90e40, t40 i/o port alternate function summary pin description (continued) ? st90e40 - st90t40 41/56
1.1 memory the memory of the st90e40 is functionallydivided into two areas, the register file and memory. the memory is divided into two spaces, each having a maximum of 65,536 bytes. the two memory spaces are separated by function, one space for program code, the other for data. the st90e40 16k bytes of on-chip eprom memory are se- lected at memory addresses 0 through 3fffh (hexadecimal) in the program space, while the st90t40 otp version has the top 64 bytes of the eprom reserved by sgs-thomson for testing purposes. the data space includes the 512 bytes of on-chip eeprom at addresses 0 through 1ffh and the 256 bytes of on-chip ram memory at memory addresses 200h through 2ffh. warning. the st90t40 has its 64 upper bytes in the internal eprom reserved for testing purpose. external memory may be addressed using the mul- tiplexed address and data buses (alternate func- tions of ports 0 and 1). at addresses greater than the first 16k of program space, the st90e40 exe- cutes external memory cycles for instruction fetches. additional data memory may be decoded externally by using the p/d alternate function out- put. the on-chip general purpose (gp) registers may also be used as ram memory for minimum chip count systems. 1.2 eprom programming the 16384 bytes of eprom memory of the st90e40 (16320 for the st90t40) may be pro- grammed by using the eprom programming boards (epb) available from sgs-thomson. 1.2.1 eprom erasing the eprom of the windowed package of the st90e40may be erased by exposureto ultra-violet light. the erasure characteristic of the st90e40 is such that erasure begins when the memory is exposed to light with a wave lengths shorter than approxi- mately 4000?. it should be noted that sunlight and some types of fluorescent lamps have wave- lengths in the range 3000-4000?. it is thus recom- mended that the window of the st90e40 packages be covered by an opaque label to pre- vent unintentional erasure problems when testing the application in such an environment. the recommended erasure procedure of the eprom is the exposure to short wave ultraviolet light which have a wave-length 2537?. the inte- grated dose (i.e. u.v. intensity x exposuretime) for erasure should be a minimum of 15w-sec/cm2. the erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 m w/cm 2 power rating. the st90e40 should be placed within 2.5cm (1inch) of the lamp tubes during erasure. figure 4. memory spaces ? st90e40 - st90t40 42/56
symbol parameter value unit v dd supply voltage 0.3 to 7.0 v av dd ,av ss analog supply voltage v ss =av ss symbol parameter test conditions value unit min. typ. max. i wpu weak pull-up current bidirectional weak pull- up, v ol =0v 50 200 420 m a i apu active pull-up current, for int0 and int7 only v in < 0.8v, under reset 80 200 420 m a i lkio i/o pin input leakage input/tri-state, 0v < v in symbol parameter test conditions value unit min. typ. max. i dd run mode current no cpuclk prescale, clock divide by 2 24mhz 40 ma i dp2 run mode current prescale by 2 clock divide by 2 24mhz 30 ma i wfi wfi mode current no cpuclk prescale, clock divide by 2 24mhz 20 ma i halt halt mode current 24mhz 50 100 m a ac electrical characteristics (v dd =5v 10% t a =40 cto+85 c, unless otherwise specified) ? st90e40 - st90t40 45/56
80-pin ceramic quad flat package with window package mechanical data 68-pin ceramic leadless chip carrier with window dim. mm inches min typ max min typ max a 3.55 0.14 a2 3.40 0.133 d 23.90 0.941 d1 20.00 0.787 d3 18.40 0.724 e 17.90 0.705 e1 14.00 0.551 e3 12.00 0.472 7.62 0.3 e 0.80 0.032 number of pins n80 nd 24 ne 16 dim. mm inches min typ max min typ max a 4.47 0.176 a1 0.89 0.035 a3 - - b 0.48 0.019 b1 - - d 25.1 0.990 d1 23.6 0.930 d3 20.3 0.800 e 25.1 0.990 e1 23.6 0.930 e3 20.3 0.800 8 0.32 e 1.27 0.050 number of pins n68 nd 16 ne 16 ? st90e40 - st90t40 46/56
sales type frequency temperature range package st90e40l0 (1) 24mhz 25 c clcc68w st90e40g0 (1) cqfp80w st90t40c6 -40 cto +85 c plcc68 st90t40q1 0 cto +70 c pqfp80 note . eprom parts are tested at 25 c only ordering information ? st90e40 - st90t40 47/56
notes: ? st90e40 - st90t40 48/56
st90r40 ? romless hcmos mcu with eeprom, ram and a/d converter (ordering information at the end of the datasheet) register oriented 8/16 bit core with run, wfi and halt modes minimum instruction cycle time:500ns (12mhz internal) romless to allow maximum external memory flexibility internal memory : ram 256 bytes eeprom 512 bytes 224 general purpose registers available as ram, accumulators or index pointers (register file) 68-lead plastic leaded chip carrier package for st90r40c dma controller, interrupt handler and serial pe- ripheral interface as standard features 40 fully programmable i/o pins up to 8 external plus 1 non-maskableinterrupts 16 bit timer with 8 bit prescaler, able to be used as a watchdog timer two 16 bit multifunction timers, each with an 8 bit prescaler and 13 operating modes 8 channel 8 bit analog to digital converter, with analog watchdogs and external references serial communications interface with asynchro- nous and synchronous capability rich instruction set and 14 addressingmodes division-by-zero trap generation versatile developmenttools, including assembler, linker, c-compiler, archiver, graphic orinted de- buggerand hardware emulators real time operating system compatible with ST9040 16k rom device (also availablein windowed and one time programma- ble eprom packages) plcc68 march 1994 49/56
pin name pin name pin name pin name 61 p44/ain4 10 p35/t1outa 43 p70/sin 60 av ss 62 p57 11 p34/t1ina 42 p71/sout 59 av dd 63 p56 12 p33/t0outb 41 p72/clkout /txclk/int4 58 p47/ain7 64 p55 13 p32/t0inb 57 p46/ain6 65 p54 14 p31/t0outa 40 p73/adtrg /rxclk/int5 56 p45/ain5 66 int7 15 p30/p/d/t0ina 55 p43/ain3 67 int0 16 a15 39 p74/p/d/int6 54 p42/ain2 68 p53 17 a14 38 p75/wait 53 p41/ain1 l 1 p52 18 a13 37 p76/wdout /busreq 52 p40/ain0 2 p51 19 a12 51 p27/rrdy5 3 p50 20 a11 36 p77/wdin /busack 50 p26/int3 /rdstb5/p/d 4 oscout 21 a10 5v ss 22 a9 35 r/w 49 p25/wrrdy5 6 oscin 23 a8 34 ds 48 p24/int1 /wrstb5 7 reset 24 a0/d0 33 as 8 p37/t1outb 25 a1/d1 32 v dd 47 p23/sdo 9 p36/t1inb 26 a2/d2 31 a7/d7 46 p22/int2/sck 30 a6/d6 45 p21/sdi/p/d 29 a5/d5 44 p20/nmi 28 a4/d4 27 a3/d3 table 1. st90r40c pin description figure 1. 68 pin plcc package ? st90r40 50/56
1.1 general description the st90r40 is a romless member of the st9 family of microcontrollers, completely developed and produced by sgs-thomson microelectron- ics using a proprietary n-well hcmos process. the romless part may be used for the prototyp- ing and pre-production phases of development, and offers the maximum in program flexibility in production systems. the st90r40 is fully compatible with the ST9040 rom version and this datasheet will thus provide only information specific to the romless device. the reader is asked to refer to the datasheet of the ST9040 rom-based de- vice. the romless st90r40 can be configured as a microcontroller able to manage external memory, or as a parallel processing element in a system with other processors and peripheral controllers. the nucleus of the st90r40 is the advancedcore which includes the central processing unit (cpu), the register file, a 16 bit timer/watchdog with 8 bit prescaler, a serial peripheral interface support- ing s-bus, i 2 c-bus and im-bus interface, plus two figure 2. block diagram cpu 1 6-bit timer / watchdog + spi sci with dma i/o port 7 (sci) 8 256 bytes register file 2 x 16-bit timer w ith dm a i/o port 3 ( timers ) 8 i/o port 0 ( address/data ) 8 i/o port 1 ( address ) 8 512 bytes eeprom 256 bytes ram i/o port 2 ( spi ) 8 i/o port 4 ( ana log inpu ts ) 8 a/d converter i/o port 5 with handshake 8 memory bus register bus vr0b1385 int0 int7 av dd av ss 8 bit i/o ports. the core has independentmemory and register buses allowing a high degree of pipe- lining to add to the efficiency of the code execution speed of the extensive instruction set. the powerful i/o capabilities demanded by micro- controller applications are fulfilled by the st90r40 with up to 56 i/o lines dedicated to memory ad- dressing or digital input/output. these lines are grouped into up to seven 8 bit i/o ports and can be configured on a bit basis under software control to provide timing and status signals, address lines, timer inputs and outputs, analog inputs, external interrupts and serial or parallel i/o with or without handshake. three memory spaces are available: program mem- ory (external), data memory (internal and external) and the register file, which includes the control and statusregisters of the on-chip peripherals. two 16 bit multifunction timers, each with an 8 bit prescaler and 13 operating modes allow simple use for complex waveform generation and meas- urement, pwm functions and many other system timing functionsby the usage of the two associated dma channels for each timer. ? st90r40 51/56
in addition there is an 8 channel analog to digital converter with integral sample and hold, fast 11 m s conversion time and 8 bit resolution. an analog watchdog feature is included for two input chan- nels. completing the device is a full duplex serial com- munications interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5mbyte/s synchronous capability (fully program- mable format) and associated address/wake-up option, plus two dma channels. 1.2 pin description as . address strobe (output, active low, 3-state). address strobe is pulsed low once at the begin- ning of each memory cycle. the rising edge of as indicates that address, read/write (r/w), and data memory signals are valid for program or data memory transfers. under program control, as can be placed in a high-impedance state along with port 0 and port 1, data strobe (ds) and r/w. ds . data strobe (output, active low, 3-state). data strobe provides the timing for data movement to or from port 0 for each memory transfer. during a write cycle, data out is valid at the leading edge of ds. during a read cycle, data in must be valid prior to the trailing edge of ds. when the st90r40 ac- cesses on-chip data memory, ds is held high dur- ing the whole memory cycle. it can be placed in a high impedance state along with port 0, port 1, as and r/w. r/w . read/write (output, 3-state). read/write de- termines the direction of data transfer for memory transactions. r/w is low when writing to program or data memory, and high for all other transactions. it can be placed in a high impedance state along with port 0, port 1, as and ds. reset . reset (input, active low). the st9 is ini- tialised by the reset signal. with the deactivation of reset, program executionbegins from the pro- gram memory location pointed to by the vector contained in program memory locations 00h and 01h. oscin, oscout. oscillator (input and output). these pins connect a parallel-resonant crystal (24mhz maximum), or an external source to the on-chip clock oscillator and buffer. oscin is the in- put of the oscillator inverter and internal clock gen- erator; oscout is the output of the oscillator inverter. av dd . analog v dd of the analog to digital con- verter. av ss . analog v ss of the analog to digital con- verter. must be tied to v ss. v dd . main power supply voltage (5v 10%) v ss . digital circuit ground. ad0-ad7, (p0.0-p0.7) address/data lines (in- put/output, ttl or cmos compatible). 8 lines pro- viding a multiplexed address and data bus, under control of the as and ds timing signals. a8-a15 address lines (output, ttl or cmos compatible) . 8 lines providing non-multiplexing ad- dress bus, under control of the as and ds timing signals. p2.0-p2.7 p3.0-p3.7, p4.0-p4.7, p5.0-p5.7, p7.0- p7.7 i/o port lines (input/output, ttl or cmos compatible). 40 lines grouped into i/o ports of 8 bits, bit programmable under program control as general purpose i/o or as alternate functions (see next section). 1.2.1 i/o port alternate functions each pin of the i/o ports of the st90r40 may as- sume software programmable alternative func- tions as shown in the pin configuration drawings. table 2 shows the functions allocated to each i/o port pins. general description (continued) ? st90r40 52/56
i/o port name function in/out alternate function port.bit p0.0 a0/d0 i/o address/data bit 0 mux 24 p0.1 a1/d1 i/o address/data bit 1 mux 25 p0.2 a2/d2 i/o address/data bit 2 mux 26 p0.3 a3/d3 i/o address/data bit 3 mux 27 p0.4 a4/d4 i/o address/data bit 4 mux 28 p0.5 a5/d5 i/o address/data bit 5 mux 29 p0.6 a6/d6 i/o address/data bit 6 mux 30 p0.7 a7/d7 i/o address/data bit 7 mux 31 p1.0 a8 o address bit 8 23 p1.1 a9 o address bit 9 22 p1.2 a10 o address bit 10 21 p1.3 a11 o address bit 11 20 p1.4 a12 o address bit 12 19 p1.5 a13 o address bit 13 18 p1.6 a14 o address bit 14 17 p1.7 a15 o address bit 15 16 p2.0 nmi i non-maskable interrupt 44 p2.1 p/d o program/data space select 45 p2.1 sdi i spi serial data out 45 p2.2 int2 i external interrupt 2 46 p2.2 sck o spi serial clock 46 p2.3 sdo o spi serial data in 47 p2.4 int1 i external interrupt 1 48 p2.4 wrstb5 o handshake write strobe p5 48 p2.5 wrrdy5 i handshake write ready p5 49 p2.6 int3 i external interrupt 3 50 p2.6 rdstb5 i handshake read strobe p5 50 p2.6 p/d o program/data space select 50 p2.7 rdrdy5 o handshake read ready p5 51 p3.0 t0ina i mf timer 0 input a 15 p3.0 p/d o program/data space select 15 p3.1 t0outa o mf timer 0 output a 14 p3.2 t0inb i mf timer 0 input b 13 p3.3 t0outb o mf timer 0 output b 12 p3.4 t1ina i mf timer 1 input a 11 table 2. i/o port alternate function summary pin description (continued) ? st90r40 53/56
i/o port name function in/out alternate function port.bit p3.5 t1outa o mf timer 1 output a 10 p3.6 t1inb i mf timer 1 input b 9 p3.7 t1outb o mf timer 1 output b 8 p4.0 ain0 i a/d analog input 0 52 p4.1 ain1 i a/d analog input 1 53 p4.2 ain2 i a/d analog input 2 54 p4.3 ain3 i a/d analog input 3 55 p4.4 ain4 i a/d analog input 4 61 p4.5 ain5 i a/d analog input 5 56 p4.6 ain6 i a/d analog input 6 57 p4.7 ain7 i a/d analog input 7 58 p5.0 i/o i/o handshake port 5 3 p5.1 i/o i/o handshake port 5 2 p5.2 i/o i/o handshake port 5 1 p5.3 i/o i/o handshake port 5 68 p5.4 i/o i/o handshake port 5 65 p5.5 i/o i/o handshake port 5 64 p5.6 i/o i/o handshake port 5 63 p5.7 i/o i/o handshake port 5 62 p7.0 sin i sci serial input 43 p7.1 sout o sci serial output 42 p7.2 int4 i external interrupt 4 41 p7.2 txclk i sci transmit clock input 41 p7.2 clkout o sci byte sync clock output 41 p7.3 int5 i external interrupt 5 40 p7.3 rxclk i sci receive clock input 40 p7.3 adtrg i a/d conversion trigger 40 p7.4 int6 i external interrupt 6 39 p7.4 p/d o program/data space select 39 p7.5 wait i external wait input 38 p7.6 wdout o t/wd output 37 p7.6 busreq i external bus request 37 p7.7 wdin i t/wd input 36 p7.7 busack o external bus acknowledge 36 table 2. i/o port alternate function summary (continued) pin description (continued) ? st90r40 54/56
1.3 memory the memory of the st90r40 is functionallydivided into two areas, the register file and memory. the memorymay optionallybe divided into two spaces, each having a maximum of 65,536 bytes. the two memory spaces are separated by function, one space for program code, the other for data. the st90r40 addresses all program memory in the external program space. the data space in- cludes the 512 bytes of on-chip eeprom at ad- dresses 0 through 1ffh and the 256 bytes of on-chip ram memory at addresses 200h through 2ffh. the external memory spaces are addressedusing the multiplexed address and data buses on ports 0 and 1. data memory may be decodedexternally by using the p/d alternate function output. the on- chip general purpose (gp) registers may be used as ram memory. figure 3. memory spaces ? st90r40 55/56
sales type frequency temperature range package st90r40c6 24mhz -40 cto+85 c plcc68 ordering information information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs- thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. ? st90r40 56/56

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